1. Field of the Invention
The present invention relates to the fields of field programmable gate array (FPGA) and emulation systems.
2. Background Information
Emulation systems for emulating circuit design are known in the art. Typically, prior art emulation systems are formed using general purpose FPGAs without integrated debugging facilities. A circuit design to be emulated is xe2x80x9crealizedxe2x80x9d on the emulation system by compiling a xe2x80x9cformalxe2x80x9d description of the circuit design, and mapping the circuit design onto the logic elements (LEs) of the FPGAs.
These general purpose FPGAs, as far as their applications to emulation systems are concerned, have a number of disadvantages. First of all, the states of signals at the nodes mapped inside the FPGAs are not directly observable, thus the term xe2x80x9chiddenxe2x80x9d nodes. Secondly, in order to be able to observe the states of signals at these xe2x80x9chiddenxe2x80x9d nodes, reconfiguration, and therefore extremely time consuming recompilation is required to bring these signals outside the FPGAs to a logic analyzer. Thirdly, a number of the FPGA I/Os will have to be consumed for bringing these signals to the logic analyzer. Furthermore, the additional signals to be routed further increase signal routing congestion. Finally, for timing sensitive applications, it is difficult to know whether the signals at these xe2x80x9chiddenxe2x80x9d nodes were read at precisely the correct time or not, if the signals are to be read in response to the occurrence of certain events, since the signals have to be brought out of the FPGAs before the read triggering events can be detected.
Thus, it is desirable to have an improved FPGA with integrated debugging facilities that is more suitable for usage by the emulation systems. As will be described in more detail below, the present invention provides for such an improved FPGA with integrated debugging facilities that achieves these and other desired results, which will be apparent to those skilled in the art from the description to follow.
An improved FPGA having integrated debugging facilities is disclosed. The improved FPGA comprises a number of enhanced logic elements (LEs) interconnected to each other, preferably, via a network of crossbars. Each enhanced LE comprises a multiple input-single output truth table and a complementary pair of master-slave latches having a data, a set and a reset input, and control logic. As a result, the enhanced LE may be used for xe2x80x9clevel sensitivexe2x80x9d as well as xe2x80x9cedge sensitivexe2x80x9d circuit design emulations. Each enhanced LE further comprises a plurality of multiplexors and buffers, allowing each LE to be individually initialized, its state to be froze momentarily, and the frozen state to be read or modified.
Additionally, the improved FPGA is further comprises a complementary context bus and read/write facilities for setting the enhanced LEs"" initial values, and for reading of their frozen states. The improved FPGA also comprises a scan register for outputting trace data for the enhanced LEs. Lastly, the improved FPGA also comprises a plurality of trigger circuitry for conditionally generating a plurality of trigger inputs.